RISC-V¶

Introduction to RISC-V fundamentals.

0x01 Architecture Characteristics¶

RISC-V is an emerging open instruction set architecture (ISA) with a high degree of flexibility and extensibility. Its core design philosophy is modularity, allowing developers to select different extension modules to build processors based on actual requirements. For example, the most basic instruction sets include RV32I and RV64I, while optional extensions cover multiplication and division (M), atomic operations (A), floating-point arithmetic (F, D), compressed instructions (C), and vector instruction sets (V) suitable for high-performance computing.

The architecture supports multiple bit widths, including 32-bit (RV32), 64-bit (RV64), and a future reserved 128-bit (RV128) mode, thus meeting diverse application scenarios from embedded systems to high-performance servers. RISC-V also explicitly distinguishes processor privilege levels, defining User mode (U-mode), Supervisor mode (S-mode), and Machine mode (M-mode), providing solid support for operating system execution and security mechanisms.

The following table lists some common instruction set extensions and their brief descriptions:

0x02 Registers¶

The RISC-V processor architecture defines a set of general-purpose registers and Control and Status Registers (CSRs) for data processing, control flow, and state information storage. Below is a brief introduction to these two categories of registers.

(1) General-Purpose Registers¶

RISC-V has a total of 32 general-purpose registers, numbered x0 through x31, each being 32-bit (RV32) or 64-bit (RV64). These registers also have corresponding ABI names commonly used in assembly language programming.

Notes: - x0 is a special read-only register that always returns 0; writes to it have no effect. - Temporary registers (t0~t6) are not guaranteed to be preserved across function calls. - Saved registers (s0~s11) must be saved and restored across function calls.

(2) CSR Registers¶

CSRs (Control and Status Registers) are important registers used for controlling, monitoring status, and configuring processor operation. In RISC-V, the CSR address space is 12 bits, supporting a total of 4096 CSR registers.

Common CSR registers include:

Notes: - CSRs can be read and written using instructions belonging to the zicsr extension instruction set, such as csrrw, csrrs, csrrc, etc. - CSRs are classified by privilege level into User-level (u), Supervisor-level (s), Machine-level (m*), etc. - In simplified implementations, supporting only Machine-mode (M-mode) CSRs is a common scenario.

(3) Floating-Point Registers¶

When the RISC-V architecture supports floating-point extensions (such as the F and D extensions), it provides a dedicated set of floating-point registers for floating-point computation and data storage.

RISC-V defines 32 floating-point registers, numbered f0 through f31, each typically being 32-bit (single precision, RV32F) or 64-bit (double precision, RV64D), depending on the implemented floating-point extension.

Notes: - The ABI naming of floating-point registers is similar to integer registers, but with the prefix f. - According to the ABI convention, function arguments are passed via fa0~fa7, and return values typically use fa0. - ft* are caller-saved, and fs* are callee-saved. - Using floating-point registers requires the processor to support the corresponding floating-point extension instruction set, such as F (single precision) or D (double precision).

0x03 Common Instructions¶

(1) Common Integer Instructions (R-Type)¶

R-type instructions are used for arithmetic or logical operations between registers, format: rd = rs1 op rs2.

(2) Common Immediate Instructions (I-Type)¶

I-type instructions perform operations on a register and an immediate value, suitable for quick computation and constant assignment.

(3) Load Instructions (I-Type)¶

Used to read data from a memory address into a register. The address is calculated from rs1 + offset.

(4) Store Instructions (S-Type)¶

Used to write values from registers into memory. The address is still calculated from rs1 + offset.

(5) Control Flow Instructions (B-Type)¶

Used to implement conditional branches, used with labels. The branch offset is a 12-bit immediate (±4KB).

(6) Jump and Link Instructions (J-Type, I-Type)¶

Used for procedure calls and function jumps, saving the return address to ra.

• If the destination register is x0, it means the return address is not saved (pure jump).
• jal is typically used for calling functions, while jalr is used for returning from functions.

(7) Special System Call Instructions (Environment Interaction)¶

0x04 Calling Convention¶

Stack frame structure (RISC-V ABI stack frame)

High Address
│
│  +-----------------------------+
│  | Saved registers              |
│  +-----------------------------+
│  | Arguments beyond register    |
│  | passing limit > a7/fa7       |
│  +-----------------------------+
│  | Return address (ra)          │
│  +-----------------------------+
│  | Local variables              |
│  +-----------------------------+
│  | (16-byte alignment padding)  |
└──► Stack pointer (sp)

1. Stack Growth¶

• Grows toward lower addresses
• sp (x2) is always kept 16-byte aligned
• sp is commonly used as a pointer to access stack contents (e.g., ld t0, 16(sp))

2. Saving Register Contents¶

Saved by callee: - s0–s11 (x8–x9, x18–x27) → Used for long-lived data - fs0–fs11 (f8–f9, f18–f27) → Floating-point saved registers - ra (x1) → Return address (saved by callee after the call pseudo-instruction modifies ra)

Saved by caller: - t0–t6 (x5–x7, x28–x31) - ft0–ft11 (f0–f7, f28–f31)

Argument Size Constraints¶

• Smaller than pointer size (e.g., char, short): Placed in the lower bits of a register
• Larger than one pointer size (e.g., long long): Requires even-aligned registers

• For example, in RV32:

  void foo(int, long long)
  

  • int → a0
  • long long → a2 and a3 (skipping a1 for even alignment)

• Larger than two pointer sizes (e.g., struct { long x[3]; }) → Passed by reference

Return Value Passing Rules¶

• Return values use:
• Integer: a0, a1
• Floating-point: fa0, fa1
• Struct returns:
• ≤2 pointer-word: Use a0/a1

• 2 pointer-word: Caller allocates memory and passes a hidden pointer as the first argument

Register Usage Overview¶

Note that sp and ra registers strictly do not belong to the scratch/preserved register classification. The handling of these two registers is mostly implemented as callee-saved. Additionally, registers like gp do not fall into this category.

References¶

• RISC-V ELF psABI Document (riscv-non-isa/riscv-elf-psabi-doc)
• RISC-V Instruction Set Architecture Official Manual (riscv/riscv-isa-manual)